1. Field of the Invention
The present invention introduces a communication apparatus designed for a constant bit rate communication and a method for securing a constant bit rate of transmission data to be transmitted over variable or constant bit rate communications networks. The variable bit rate communications network includes an Asynchronous Transfer Mode (ATM) network and the like over which various types of data travel in a fixed-length packet format, and the constant bit rate communications network includes telephone line networks, communication satellite circuit networks and the like.
2. Description of the Related Art
In the Asynchronous Transfer Mode (ATM) representing a data transmission technique implemented in a broadband Integrated Services Digital Network (ISDN), for example, various types of media data having different characteristics such as video data, audio data, information data and the like are transmitted in a uniform length cell format of 53 bytes. In the ATM network, data are allowed to be transmitted at any bit rate within a maximum transfer capacity of the network under the condition that a maximum output cell rate, an average cell rate and the like are to be declared. This type of communication with a communication bit rate varying with time is called a variable bit rate communication and another type with the communication bit rate being constant is called a constant bit rate communication.
In a network over which data are transferred in a cell format such as the ATM network and the like, there exists a transport time lag (referred to as xe2x80x9ca delay variationxe2x80x9d hereinafter) between transmitting and receiving stations so that a transmission timing of transmission data at a transmitting station cannot be used at a receiving station. Then, it has been a general practice of eliminating the delay variation that data transmitted on a constant bit rate basis are temporarily stored in a variation absorbing buffer at a receiving station so as to smooth over the variation.
Conventionally, a constant bit rate communication can be achieved by controlling a transmission interval of cells to be transmitted over the network from a line interface.
A conventional system for achieving a constant bit rate in data transmission is disclosed by Japanese Unexamined Patent Publication No. 212544/1992. FIG. 18 shows a block diagram of an ATM packet adapter apparatus utilizing the rate control technique of the conventional system.
A conventional art to which the present invention is directed is discussed below with the conventional system being cited.
Referring to FIG. 18, an ATM packet adapter apparatus E1, transmission First-In First-Out (FIFO) units E2a through E2d, cell assembling units E3a through E3d, a call controller E4, a line interface (I/F) unit E5, terminals E6a through E6b with no ATM interface, a cell multiplexing bus E7, and a control bus E8 within the ATM packet adapter apparatus E1 (referred to as the control bus E8 hereinafter) are shown. The transmission FIFO units E2a through E2d, the cell assembling units E3athrough E3d, and the terminals E6a through E6b may be generically referred to, respectively, as a transmission FIFO unit E2, a cell assembling unit E3, and a terminal E6 hereinafter.
The ATM packet adapter apparatus E1 receives data from the terminal E6a, E6b, E6c at the cell assembling unit E3b, E3c, E3d, respectively, where the data are assembled to obtain cell data. The cell data are transferred to the transmission FIFO unit E2b, E2c, E2d to be stored temporarily. Meanwhile, the call controller E4 declares a maximum throughput of the data outputted from the terminal E6a, E6b, E6c to an ATM switching system through a call control sequence. The transmission FIFO unit E2b, E2c, E2d outputs the cell data according to a cell output interval being set based upon a maximum throughput determined by the call control sequence.
The call controller E4, upon reception of a call request from the terminal E6, declares a maximum throughput for the call request to the ATM network via the cell assembling unit E3a, the transmission FIFO unit E2a, the cell multiplexing bus E7 and the Line I/F unit E5. When the maximum throughput is accepted, the call controller E4 determines the maximum throughput as a maximum throughput for transmission.
The cell data from the terminals E6a through E6coutputted from the transmission FIFO units E2b through E2d are supplied to the multiplexing bus E7 to be multiplexed, and multiplexed cell data are transferred to the line I/F unit E5 for interfacing with the ATM network and transmitted over the ATM network.
FIG. 19 shows a block diagram illustrating the configuration of the transmission FIFO unit E2. Referring to the figure, an FIFO buffer E9 stores cell data from the cell assembling unit E3 temporarily, and an FIFO write controller E11 and an FIFO readout controller E12 control writing and reading, respectively, of the cell data in the FIFO buffer E9. The FIFO write controller E11, upon reception of the cell data from the cell assembling unit E3, detects the presence of the cell data and supplies a write signal WR to the FIFO buffer E9, and at the same time, supplies an FIFO data presence signal DP to a cell multiplexing bus controller E13. The cell multiplexing bus controller E13 provided for an arbitration control of the cell multiplexing bus E7 outputs a bus request (signal) BR to the cell multiplexing bus E7, and when receiving a bus grant (signal) BG in response, outputs a read start signal RDS to the FIFO readout controller E12.
A transmission interval controller E10 provided in the transmission FIFO unit E2 receives control information such as a set value for an input interval, the address data of the transmission FIFO unit E2, control data and the like from the call controller E4 via the control bus E8.
The transmission interval controller E10 controls the cell output interval of the cell data to be outputted to the cell multiplexing bus E7 so as to have the interval being longer than the set value. The transmission interval controller E10 includes a control bus I/F unit E14 for interfacing with the control bus E8, a transmission interval setting register E15 for latching the set value included in the control information, and a transmission interval counter E16 for counting down from the set value as an initial value. The transmission interval counter E16 outputs a count zero signal CZ indicating an end of counting to the cell multiplexing bus controller E13 when a counting is completed.
FIG. 20 shows a block diagram illustrating the configuration of the transmission interval controller E10. The control bus I/F unit E14 includes an address comparator E17 and a control bus controller E18. The control bus E8 here is assumed to include an eight-bit data bus for transmitting various types of control data, a 16-bit address bus for transmitting the address of each unit in the ATM packet adapter apparatus E1, and a control bus for transmitting a control signal (CS). The transmission interval controller E10 receives at the transmission interval setting register E15 a set value based upon a maximum throughput from the call controller E4 via the data bus, an address via the address bus at the address comparator E17, and the control signal CS via the control bus at the control bus controller E18. The address comparator E17 compares a received address with a self address to detect a matching of the received address with the self address of the transmission FIFO unit E2, and outputs a matching signal MS to the control bus controller E18 when detecting the matching. The control bus controller E18, based upon the matching signal MS and the control signal CS, outputs a data latch signal DL to the transmission interval setting register E15. The transmission interval setting register E15 latches the set value supplied via the data bus at an input timing of the data latch signal DL.
The operation of the thus configured conventional ATM packet adapter apparatus is now described. FIG. 21 is an output timing chart of cell data outputted to the cell multiplexing bus E7. FIG. 22 is a diagram illustrating a relation between transmission interval and throughput.
Upon reception of a call request issued from the terminal E6, the call controller E4 declares a maximum throughput for the call request to the ATM network via the cell assembling unit E3a, the transmission FIFO unit E2a, the cell multiplexing bus E7, and the line I/F unit E5. When the call request is accepted by the receiver, the call controller E4 determines the declared maximum throughput as a maximum throughput for transmission.
With the maximum throughput being determined, a set value for a transmission interval is set based upon the determined maximum throughput. For example, when the maximum throughput is set to 77.76 Mbps, then the set value is xe2x80x9c52xe2x80x9d because the transmission interval takes 53 clocks, as shown in FIG. 22(a). When the maximum throughput is set to 38.88 Mbps, which requires a declaring, the set value is xe2x80x9c158xe2x80x9d because the transmission interval takes 159 clocks, as shown in FIG. 22(b). The following expression calculates a clock S for the transmission interval, where TP denotes the maximum throughput.
S=(155.52xc3x9753)/TPxe2x88x9253
The set value for the transmission interval is obtained by subtracting 1 from a calculated value of the clock S in the call controller E4.
With the maximum throughput of the terminal E6 being set to 77,76 Mbps, for example, the minimum length of 53 clocks is required for the transmission interval, as shown in FIG. 22(a). In this case, the call controller E4 determines that a value xe2x80x9c52xe2x80x9d is to be set as the set value in the transmission interval controller E10 for the transmission interval.
Specifically, the call controller E4 outputs an address of the transmission FIFO unit E2b to the address bus of the control bus E8. When the address of self is detected at the address comparator E17 in the control bus I/F unit E14 and the control bus controller E18 detects the matching signal MS, the data latch signal DL is outputted to the transmission interval setting register E15. When a value xe2x80x9c52xe2x80x9d is outputted to the data bus in the control bus E8, the value xe2x80x9c52xe2x80x9d is given for the set value for the transmission interval at the transmission interval setting register E15.
A flow of cell data is now described. Data outputted from the terminal E6a are assembled to obtain cells of 48 bytes with each cell adding an ATM header of five bytes to form cell data at the cell assembling unit E3b. The cell data outputted from the cell assembling unit E3b are written into the FIFO buffer E9 in the transmission FIFO unit E2b by the FIFO write controller E11.
The FIFO write controller E11 outputs the FIFO data presence signal DP to the cell multiplexing bus controller E13 whereby a bus request/grant sequence with the bus request signal BR and the bus grant signal BG is carried out for outputting the cell data to the cell multiplexing bus E7.
When the cell data are outputted from the FIFO buffer E9, the FIFO readout controller E12 outputs a read completion signal RDC xe2x80x9cLxe2x80x9d to the transmission interval controller E10 at a load input of the transmission interval counter E16.
Upon reception of the read completion signal RDC xe2x80x9cLxe2x80x9d, the transmission interval counter E16 loads the value set xe2x80x9c52xe2x80x9d latched in the transmission interval setting register E15 as load input data and starts counting.
With a counted value xe2x80x9c0xe2x80x9d, the transmission interval counter E16 outputs the count zero signal CZ xe2x80x9cLxe2x80x9d to the cell multiplexing bus controller E13, which triggers the bus request/grant sequence for outputting the cell data to the cell multiplexing bus E7. Subsequently, in the line I/F unit E5, the cell data are converted from an electric signal into a light signal to be transmitted over the ATM network.
The conventional art of the present invention has thus been described with Japanese Unexamined Patent Publication No. 212544/1992 being cited.
As aforementioned, the conventional ATM packet adapter apparatus is provided with the transmission interval control of cell data alone for obtain a constant bit rate communication. This poses the problem that a terminal can output data at any bit rate within a maximum throughput. As a result, a constant bit rate communication cannot be secured in an accurate manner with a generated amount of transmission data unstable with time, which prevents the variation absorbing buffer from absorbing the delay variation to be eliminated. A need then exists for securing a constant bit rate communication in an accurate manner so as to achieve the absorption of the delay variation by the variation absorbing buffer.
The present invention is directed to solving the foregoing problems. A primary object of the present invention is to introduce an apparatus and method for achieving a constant bit rate communication with a line interface unit for interfacing with a network line controlling the bit rate of transmission data outputted from a data source so as to secure a constant bit rate.
Another object of the present invention is to achieve a constant bit rate communication so as to eliminate the delay variation caused in the ATM network. Furthermore, another object of the present invention is to realize an apparatus and method for transmitting data at a constant bit rate over a constant bit rate communication network such as a telephone line network, a communication satellite circuit network or the like.
These and other objects are accomplished by the present invention as hereinafter described in further detail.
According to one aspect of the present invention, a rate control communication apparatus for transmitting data over a communication network includes an information source inputting unit for receiving information source data to be transmitted, an information source processing unit for processing the information source data to generate transmission data in a predetermined data format, and a line interface unit for outputting a transmission enable signal indicating a transmission enable status of the transmission data to the information source processing unit so as to have the transmission data outputted from the information source processing unit, receiving the transmission data, and transmitting the transmission data over the communication network.
The line interface unit may include a transmission control unit for calculating an output interval of the transmission enable signal and outputting the transmission enable signal to the information source processing unit based upon a calculated output interval.
The information source processing unit may include a media multiplexer for multiplexing the information source data received from the information source inputting unit.
The information source inputting unit may include an information source encoder for encoding the information source data.
The information source processing unit may temporarily store the transmission data to be outputted to the line interface unit, and the information source processing unit may generate and output dummy data alone to the line interface unit when an amount of the transmission data temporarily stored to be outputted to the line interface unit is less than a predetermined amount.
The information source processing unit may include a transmission request signal generator for generating a transmission request signal indicating a request for the transmission enable signal when the amount of the transmission data is more than the predetermined amount and outputting the transmission request signal to the line interface unit, and the line interface unit may monitor and detect a reception of the transmission request signal.
The line interface unit may output the transmission enable signal to the information source processing unit when detecting the reception of the transmission request signal, and output a dummy data transmission indication signal indicating a request for transmitting the dummy data when detecting no reception of the transmission request signal, and the information source processing unit may output the transmission data to the line interface unit upon reception of the transmission enable signal and output the dummy data to the line interface unit upon reception of the dummy data transmission indication signal.
The line interface unit may generate and transmit dummy data over the communication network when detecting no reception of the transmission request signal.
The information source processing unit may output a first control signal to the information source inputting unit so as to reduce a receiving amount of the information source data when storing the transmission data generated in more than the predetermined amount to be outputted to the line interface unit and output a second control signal to the information source inputting unit so as to increase the amount of the information source data to be received when storing the transmission data generated in less than the predetermined amount.
The information source processing unit may include a plurality of information source processing units, and the line interface unit may output a plurality of transmission enable signals respectively to the plurality of information source processing units, and the line interface unit may monitor an amount of the transmission data generated in each of the plurality of information source processing units through receptions of transmission request signals respectively from the plurality of information source processing units and output one of the plurality of transmission enable signals to a corresponding one of the plurality of information source processing units at a certain timing.
The rate control communication apparatus may further include a transmission data multiplexing bus for receiving a plurality of transmission data outputted from the plurality of information source processing units and multiplexing the plurality of transmission data.
The line interface unit may allocate outputs of the transmission enable signals to the plurality of information source processing units so as to have a transmitting frequency of each of the plurality of transmission data from the plurality of information source processing units fixed.
The line interface unit may allocate outputs of the plurality of transmission enable signals to the plurality of information source processing units based upon a transmitting priority assigned to each of the plurality of information source units, the transmitting priority indicating a transmitting order among the plurality of transmission data.
The line interface unit may monitor receptions of the transmission request signals from the plurality of information source processing units to recognize a generation characteristic of each of the plurality of transmission data, and change an output allocation of the plurality of transmission enable signals to corresponding information source processing units dynamically based upon the generation characteristic.
The line interface unit may change the transmitting priority assigned to each of the plurality of information source processing units dynamically.
The information source processing unit may store low priority transmission data to be transmitted through a line when a communication band is not fully occupied by transmission data, and the line interface unit may transmit the low priority transmission data through the line when the communication band is not fully occupied by transmission data.
According to another aspect of the present invention, a rate control communication method for transmitting data over a communication network includes the steps of inputting information source data to be transmitted, processing the information source data to generate transmission data in a predetermined data format, and line interfacing for outputting a transmission enable signal indicating a transmission enable status of the transmission data generated in the processing step so as to have the transmission data outputted, receiving the transmission data, and transmitting the transmission data to the communication network.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.